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for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 1 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll features functional diagram ? fractional or i nt eger modes ? 14 ghz, 16-bit r f n - c ou nter ? 24-bit step size r es olution, 6 hz typ ? ultra low phase n oi se 12 ghz, 50 mhz r ef . -98 / -103 dbc/hz @ 20 khz (frac / i nt eger) ? r eference path i np ut: 200 mhz ? 14-bit r eference path divider ? low fractional spurious ? r eference spurs: -90 dbc typ ? a uto and t ri ggered sweeper functions ? c ycle slip prevention ( c sp ) for fast settling ? a uxiliary c lo ck source ? 40 lead 6x6mm sm t p ackage: 36mm2 typical applications ? base stations for mobile r ad io (gsm, p c s, d c s, c dm a , w c dm a ) ? wireless l an s, wimax ? c ommunications t es t equipment ? cat v equipment ? fm c w sensors ? a utomotive r ad ar ? phased- a rray systems information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 2 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 1. electrical specifcations parameter c onditions / n ot es min t yp max units prescaler characteristics max r f i nput frequency (3.3v) 12 14 ghz max r f i nput frequency (2.7 - 3.3v) 12 13 ghz min r f i nput frequency 0.1 mhz r f i nput power fmin10 ghz -10 0 -6 10 dbm 16-bit n -divider r an ge ( i nt eger) 16-bit divider and fxed divide-by-2 step of 2 64 131,070 16-bit n -divider r an ge (fractional) fraction n om inal divide ratio varies (-6 / +8) dynamically max 72 131,062 ref input characteristics max r ef i nput frequency (pin x r ef p) 250 mhz max r ef i nput frequency (pin xs in ) 250 mhz min r ef i nput frequency xs in m inimum 20mhz due to phase noise degradation 100 khz r ef i nput voltage r an ge (pin x r ef p) ac c o upled 1.5 2.0 3.3 vpp r ef i nput power r an ge (pin xs in ) 50 ? source -6 0 12 dbm r ef i nput c apa citance 5 pf 14-bit r -divider r an ge 1 16,383 general description t he hm c 702lp6 c e is a s ige bi c m o s fra ctional- n p ll. t he fr actional- n p ll includes a fxed divide by 2 followed by a 8ghz 16-bit r f n -d ivider, a 24-bit delta-sigma modulator, a very low noise digital phase frequency detector (pfd), and a precision controlled charge pump. t he fractional- n p ll features an advanced delta-sigma modulator design that allows ultra-fne frequency step sizes. t he fractional- n p ll features the ability to alter both the phase-frequency detector (pfd) gain and the cycle slipping characteristics of the pfd. t hi s feature can reduce the time to arrive at the new frequency by 50% vs. conventional pfds. ultra low in-close phase noise also allows wider loop bandwidths for faster frequency hopping. t he fractional- n p ll contains a built-in linear sweeper function, which allows it to perform frequency chirps with a wide variety of sweep times, polarities and dwells, all with an external or automatic sweep trigger. i n addition the fractional- n p ll has a number of auxiliary clock generation modes that can be accessed via the gp o . electrical specifcations, t a = +25c v cc hf = v cc p r s = r vdd = +3.3v vpp c p = v cc oa = v ddpd r = v ppd r v = vd dpd = vddpdv = +5v dvdd = dvdd io = d vddq = +3.3v g n dd r v = g n d c p = g n d pd = g n d pdv = g n d pd r = 0 v information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 3 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 1. electrical specifcations parameter c onditions / n ot es min t yp max units phase detector fractional mode phase detector frequency 0.1 70 mhz i nteger mode phase detector frequency 0.1 100 mhz charge pump max o utput c ur rent 4 m a min o utput c ur rent 125 a c harge pump gain step size (5-bits) 125 a c harge pump t ri m step size (3-bits) 14 a c harge pump o ff set step size (4-bits) 29 a pfd / c harge pump n oi se ( i nt eger) 6 ghz, 50 mhz r ef , i np ut referred 1 khz -141 dbc/hz 10 khz -149 dbc/hz 100 khz -155 dbc/hz c ompliance voltage less than 3 db degradation typ. at these limits -406 a o ff set 0.4 vpp c p-0.8 v -406 a o ff set 0.8 vpp c p-0.4 v logic inputs v i h i nput high voltage vdd io -0.4 v v i l i nput low voltage 0.4 v logic outputs v i h o utput high voltage vdd io - 0.1 v v i l o utput low voltage 0.1 v power supply voltages v cc - a nalog 3v supplies v cc p r s, r vd d, v cc hf 3 3.3 3.45 v dvdd - digital i nt ernal supply dvdd, dvddq 3 3.3 3.45 v dvdd io - d igital i /o s upply dvdd io 3 3.3 3.45 v a nalog 5v supplies v ccoa , vpp c p, v ppd r v, vddpd, vddpdv, vddpd r 4.5 5.0 5.5 v power supply current (6 ghz fractional mode, 50 mhz pfd) a nalog +5v v ccoa , vpp c p, v ppd r v, vddpd, vddpdv, vddpd r 26 m a a nalog +3.3v v cc p r s, r vd d, v cc hf 116 m a digital +3.3v dvdd, dvdd io , dv ddq 19 m a power down - c ry stal o ff r eg 01h = 0 c rystal not clocked 10 a power down - c ry stal o n, 1 00 mhz r eg 01h = 0 c rystal clocked 100 mhz 20 200 a temperature sensor (3-bit) min t emperature r eadout: 000 -32 c (continued) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 4 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 1. electrical specifcations parameter c onditions / n ot es min t yp max units max t emperature r ead out: 111 +82 c t emp c hange / lsb 17. 5 c / lsb worst c ase a bs olute t em p error 10 c c urrent c on sumption (when enabled) 2 m a power on reset a ll digital inputs must be <0.7v prior to application of power for proper reset t ypical r eset voltage on dvdd 700 mv min dvdd voltage for n o r es et 1.5 v closed loop phase noise 12 ghz v co , i nt eger, 100 mhz pfd 1 khz offset -96 dbc/hz 12 ghz v co , i nt eger, 100 mhz pfd 10 khz offset -105 dbc/hz 12 ghz v co , i nt eger, 100 mhz pfd 100 khz offset -111 dbc/hz 12 ghz v co , fr actional, 50 mhz pfd 1 khz offset -92 dbc/hz 12 ghz v co , fr actional, 50 mhz pfd 10 khz offset -98 dbc/hz 12 ghz v co , fr actional, 50 mhz pfd 100 khz offset -103 dbc/hz closed loop phase noise n ormalized to 1 hz i nteger mode measured with 50 mhz pfd -227 dbc/hz fractional mode measured with 50 mhz pfd -221 dbc/hz (continued) table 2. absolute maximum ratings parameter rating r vdd, v cc hf , dvdd, dvddq, v cc p r s -0.3 to +3.6v v ccoa , vpp c p, v ppd r v, v ddpd, vddpdv, vddpd r , d vdd io -0.3 to +6v o perating t em perature -40 to +85 c storage t emperature -65 to +120 c maximum junction t em perature +125 c t hermal resistance ( r th ) (junction to ground paddle) 25 c / w r efow soldering peak t emperature 260 c t ime at peak t em perature 40 sec esd sensitivity (hbm) c lass 1b stresses above those listed under a bs olute maximum r atings may cause permanent damage to the device. t h is is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 5 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 3. pin description pin n o. pin n ame p i n t y pe description 1 v cc p r s supply r f prescaler power supply. n om inally +3.3v 2 v ccoa supply c hargepump o p a mp power supply. n om inally +5v 3 vpp c p supply power supply for c har ge pump. n om inally +5v 4 c p a nalog o /p c harge pump output 5 g n d c p g n d power supply g n d fo r c ha rge pump 6 g n d d r v g n d c harge pump g n d 7 vppd r v supply power supply for c ha rge pump, n om inally +5v 8 vddpd supply power supply for phase detectors, n om inally +5v 9 g n d pd g n d power supply g n d fo r phase detector 10, 20, 21 n / c n / c n o c on nection 11 vddpdv supply power supply for phase detector v co p ath, n om inally +5v 12 g n d pdv g n d power supply g n d fo r phase detector v co p ath 13 vddpd r supply power supply for phase detector r ef p ath, n om inally +5v 14 g n d pd r g n d power supply g n d fo r phase detector r ef p ath 15 x r efp a nalog i /p square wave c ry stal r ef i np ut 16 r vdd supply power supply for r ef path, n om inally +3.3v 17 xs in a nalog i /p sinusoidal c ry stal reference input 18 r ef c a p a nalog i / o r eference path bypass 19 r s t b c m o s i /p r eset i nput (active low). c yc le low for > t re f to reset. r ec ommended after power-up 22 dvdd supply digital power supply, n om inally +3.3v 23 gp o 1 d o general purpose o utput 1 with t ri state 24 gp o 2 d o general purpose o utput 2 with t ri state 25 gp o 3 d io general purpose i nput / o utput with t ri state may be confgured for external r am p trigger i np ut. see register r eg 1 4h[5] 26 dvddq supply quiet supply, n om inal +3.3v, zero c ur rent 27 se n c m o s i /p main serial port enable input 28 sd i c m o s i /p main serial port data input 29 s c k c m o s i /p main serial port clock input 30 vsle d o leave pin disconnected. 31 vsd o d o leave pin disconnected. 32 vs c k d o leave pin disconnected. 33 ld_sd o c m o s o /p lock detect or main serial port data o ut put 34 dvdd io supply power supply for digital i / o , ma tches external digital supply in 1.8v to 5.5v range 35 dvdd supply i nternal digital power supply. n om inally 3.3v 36 g n dh f g n d ground for r f 37 v coin r f i /p i nput to the r f pr escaler 38 g n dh f g n d ground for r f i np ut 39 v cc hf supply r f section power supply. n om inally 3.3v 40 b ia s a nalog i /p decoupling pin for r f se ction, nominally external 1nf bypassed to v cc hf information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 6 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll typical phase noise typical phase noise @ 30 khz offset - fractional mode rf divider sensitivity frequency sweep cycle slip prevention: frequency hop from 5200 mhz to 3950 mhz typical max frequency vs. temperature -6 dbm, 3.3v -110 -108 -106 -104 -102 -100 -98 -96 4000 6000 8000 10000 12000 14000 output frequency (mhz) phase noise (dbc/hz) hmc586lc4b vco hmc587lc4b vco hmc508lp5e vco hmc588lc4b vco hmc513lp5e vco hmc515lp5e vco hmc529lp5e vco 3900 4100 4300 4500 4700 4900 5100 5300 -10 0 10 20 30 40 50 60 70 time (us) csp on csp off frequency (mhz) -110 -100 -90 -80 -70 -60 13000 13500 14000 14500 15000 15500 frequency (mhz) 30khz offset, -40c 30khz offset, +25c 30khz offset, +85c phase noise (dbc/hz) divider failure +85c divider failure +25c divider failure -40c 5850 5900 5950 6000 6050 6100 6150 -2 -1 0 1 2 3 time (ms) frequency (mhz) -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 100 1000 10 4 10 5 10 6 10 7 10 8 frequency (hz) phase noise (dbc/hz) integer mode 13ghz, 100mhz pfd with hmc584 vco typ fom -228 dbc frac mode 12ghz, 50mhz pfd with hmc582 vco typ fom -221dbc -40 -30 -20 -10 0 10 0 2000 4000 6000 8000 10000 12000 14000 frequency (mhz) sensitivity (dbm) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 7 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll 1. r eference path i np ut buffers 2. r eference path divider 3. v co p ath i np ut buffer 4. v co p ath multi-modulus prescaler/divider 5. ? fractional modulator 6. phase frequency detector 7. c harge pump 8. main serial port 9. a uxiliary serial port 10. t emperature sensor 11. power o n r es et c ir cuit 12. c w sweeper subsystem 13. a uxiliary c lo ck generator 14. general purpose o ut put (gp o ) bu s 15. multiple v co c on troller theory of operation t he hm c 702lp6 c e s ynthesizer consists of the following functional blocks each of these blocks is described briefy in the following section. reference path t he full r ef erence path block diagram is shown in figure 1. t he u ltra low noise phase detector requires the best possible reference signal. since a given application may desire to use a square wave or a 50 o hm s inusoidal crystal source, hm c 70 2lp6 c e of fers two input ports, each one optimized for the lowest possible noise for the source type being used. for absolute best low noise performance, the sine wave path should be used. t he user should use only one r ef p ath input, that is the input that matches their reference source type. n ot e the input is defaulted to the square wave input on power up. should the sine reference path be used, it is necessary to enable the sine input, shut down the square wave input and set the mux ( rfp_buf_sin_en=1, rfp_buf_sq_en=0, rfp_buf_sin_ sel=1 , t able 7 ). t he unused port should be left open. t he reference path supports input frequencies of up to 250 mhz typical, however the maximum frequency at the phase detector (pfd) depends upon the mode of operation, worst case at +85 c , 7 0 mhz in fractional mode and 100 mhz in integer mode. hence reference inputs of greater than the pfd maximum frequency must use the appropriate r divider setting. figure 1. reference sine input stages t he unused reference port is normally not connected. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 8 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll sine reference input t he crystal reference sine input stage is shown in figure 2. t hi s is the lowest noise reference path. t hi s is a common emitter single ended bipolar buffer. t he x s in i nput pin is d c c oupled and has about 950 mv bias on it. expected input is a 0 dbm sinusoid from a 50 o hm s ource. n or mally the input should be a c c oupled externally. t he s ine buffer input impedance is dominated by a 25 o hm s hunt resistor in series with a 50 pf on chip cap. should a lower input impedance be needed, an external 50 o hm s hunt resistor can be used, d c i solated by an external bypass cap. t he sine input reference path phase noise foor is approximately equivalent to -159 dbc/hz. for best performance care should be taken to provide a crystal reference source with equivalent or better phase noise foor. figure 2. ref sine input square wave reference input t he square wave r ef i np ut stage is shown in figure 3. t he s tage is designed to accept square wave inputs from c ml to c m o s levels. slightly degraded phase noise performance may be obtained with quasi sine 1 vpp inputs. i t ma y be necessary to attenuate very large c m o s le vels if absolute best in close phase noise performance is required. i np ut reference should have a noise foor better than -160 dbc/hz to avoid degradation of the input reference path. figure 3. square wave ref input stage information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 9 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll reference path r divider t he referenced path features a 14-bit divider ( rfp_div_ratio, reg03h<13:0> t able 9 ) and can divide input signals at up to 250 mhz by numbers from 1 to 16,383. t he s elected input reference source may be divided or bypassed ( rfp_div_select ), and applied to the phase detector reference input. reference path test features a fractional synthesizer is a complex combination of a low phase noise analog oscillator running in close proximity with a nearly randomly modulated delta-sigma digital modulator. c lean spur free operation of the synthesizer requires proper board layout of power and grounds. spurious sources are often difficult to identify and may be related to harmonics of the digital modulation which land near the operating frequency of the v co , or t hey may arise from repeating patterns in the digital modulation itself . t he l oop flter and the fractional modulator are designed to suppress these fractional spurs, but it is sometimes the case that the isolation of the spurious products comes from layout issues. t he p roblem is how to identify the sources of spurious products if they occur? t he reference path of the hm c 70 2lp6 c e fe atures some interesting test options for clocking the digital portion of the synthesizer which may provide for a better understanding of the source of reference spurs should they occur. see figure 4 , t able 7 and t able 24 for more register details. for normal operation, r eg 3h[15]=1. when r eg 3h[15]=1, (rfp_auto_refdiv select enabled) then r eg 3 [ 14] & r eg 1 [ 2] are ignored. i f r eg 3 [ 13:0] is programmed to >=2, r efd iv will be enabled and the divided output will be fed to the pfd. i f r eg 3 [13:0] is programmed to 1, r efd iv will be disabled and the undivided reference signal will be fed to the pfd. when r eg3h[15]=0 (rfp_auto_refdiv select disabled), then the state of the r efd iv is controlled by r eg 3 [ 14] & r eg 1 [2]. t hen to enable r efd iv r eg 1 [ 2] = 1. t o pa ss the divided reference signal to the pfd, r eg 3 [ 14]=1. i f r eg 3 [14]=0, the undivided reference is passed directly to the pfd. t hi s confguration would typically only be used for engineering test. i t al lows the r efd iv to be running while the pfd is operating with the undivided reference. t hi s allows inspection for spurs that may be manifest from the divider running. i t is possible for example to set the synthesizer to integer mode of operation, where the digital harmonics normally fall directly on the v co fr equency. we might chose for example to use the sine source ( rfp_buf_sine_sel=1, div_ todig_en=0 ) to drive the reference divider. i n su ch a case the delta sigma modulator is not normally used, however if we wish to test the effects of the digital power supply isolation, we could input a 2 nd reference source on the square wave input, enable its buffer ( rfp_buf_sq_en=1 ), and enable the 2 nd crystal to clock the unused delta sigma modulator ( sqr_todig_en=1 and dsm_xref_sin_select=0 ). t his would allow the square wave clock to be set independently of the locked integer mode v co , an d hence measure the coupling of the digital to the sidebands of the v co a t various frequencies. such a test can help in identifying and debugging grounding and layout issues in the application circuit related to the digital portion of the p c b sh ould they occur. i n ge neral it is recommended to follow the suggested layout closely to avoid any such problems. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 10 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll figure 4. reference path block diagram vco path t he r f path from the v co to t he phase detector, is referred to as the v co p ath. t he v co p ath consists of an input isolation buffer and a multi-modulus prescaler, or simply the n divider. t he n d ivider is controlled by the fractional modulator. t hi s path operates with inputs directly from the external v co . rf input stage t he synthesizer r f in put stage routes the external v co to t he phase detector via a 16-bit fractional divider. t he i nput is protected by esd diodes as shown in figure 5. figure 5. rf input stage information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 11 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll rf path n divider t he main r f pa th divider including a fxed divide-by-2, is capable of average divide ratios of even numbers between 131,062 and 72 in fractional mode, and 131,070 to 64 in integer mode. t he r eason for the difference between integer and fractional modes is that the fractional divider actually divides by up to 4 from the average divide number. a ct ual division ratios when used with a given v co w ill depend upon the reference frequency used and the desired output band. general purpose output (gpo) interface t he hm c 70 2lp6 c e fe atures a 3-wire general purpose o ut put (gp o ) in terface. gp o r egisters are described in reg1bh t able 32 . t he gp o i s a fexible interface that supports a number of different functions and real time waveform access including: a. general data o ut put from sp i r egister gpo_sel_0_ data (gpo_ sel=0) b. prescaler & reference path outputs (gpo_ sel=1) c. lock detect windows (gpo_ sel=2) d. a nt i-cycle slip waveforms (gpo_ sel=3) e. i nt ernal synchronized frac strobe with clocks (gposel=4) f. ? modulator phase a cc umulator (gposel=6) g. a ux iliary oscillators (gposel=7) h. multiple v co c on trol, latch enables (gposel=9) i. ? modulator o ut puts (gposel=10) general data to gpo (gpo_sel=0) setting register gpo_sel=0 in t able 32 assigns the 3-bit data from register gpo_sel_0_data reg1b<6:4> to the gp o bus. prescaler and reference path outputs (gpo_sel = 1) setting register gpo_ sel=1 ( reg1b<3:0> t able 32 ) results in the input crystal being buffered out to gp o 3 a s shown in figure 6. t hi s is useful for example to generate a copy of the input crystal signal to drive other circuits in the application, while at the same time isolating the noisy circuits from the sensitive crystal output. o ft en only the synthesizer requires very low phase noise from the crystal, hence it is desirable to isolate other circuits from the crystal itself and allow the synthesizer sole use of the low phase noise crystal. gpo_ sel=1 also routes the 250 mhz 14-bit reference path divider to gp02 and the 16-bit 14 ghz v co p ath prescaler output to gp01. t hi s option allows the synthesizer to function as a stand alone fractional or integer prescaler and provides visibility into the prescaler and reference path timing for sensitive applications. figure 6. gpo_01 outputs information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 12 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll lock detect windows (gpo_sel=2) setting register gpo_sel = 2 ( reg1bh<3:0> t able 32 ) results in the lock detect window (figure 12) and the phase frequency detector up and d n o utput control signals (figure 15) to be routed to pins gp o 1, g p o 3 an d gp o 2 respectively. t hi s option gives insight into the lock detection process and could allow the synthesizer to be used with an external charge pump. figure 7. gpo_02 outputs anti-cycle slip waveforms (gpo_sel = 3) setting register gpo_sel=3 ( reg1bh<3:0> t able 32 ) gives visibility into the anti-cycle slipping function of the pfd as described in section cycle slip prevention ( c sp). t hree waveforms, reference path freq > v co p ath freq, vco path freq > ref path freq, and a pfd strobe which holds the pfd at maximum gain, are routed to gp o 3, g p o 2, a nd gp o 1 respectively. t he se lines will be active during frequency pull-in and will indicate instantaneously which signal, reference or vco path is greater in frequency. t he p fd strobe gives insight into when the pfd is near maximum gain at 2. t he pfd strobe will be active until the v co p ulls into lock. internal synchronized frac strobe with clocks (gpo_sel= 4) setting register gpo_sel=4 in ( reg1bh<3:0> t able 32 ) gives visibility into the internally synchronized strobe that is generated when commanding a frequency change by writing to the frac register. t he i nternal strobe initiates the update to the fractional modulator. t he i nternal frac strobe, the ref path divider output and the sine reference input are buffered out to gp o 1, g p o 2 an d gp o 3 re spectively as shown in figure 8. i n th is mode, gp o 1 ma y be used to trigger an external instrument when doing frequency hopping tests for example. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 13 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll figure 8. gpo_04 outputs modulator phase accumulator (gpo_sel=6) setting register gpo_sel=6 ( reg1bh<3:0> t able 32 ) assigns the three msbs of the delta sigma modulator frst accumulator to gp o <3 :1> , where gp o 3 is t he msb. t hi s feature provides insight into the phase of the v co . auxiliary oscillators (gpo_sel=7) setting register gpo_sel=7 ( reg1bh<3:0> t able 32 ) assigns an auxiliary clock, an internal ring oscillator, and the internal sigma delta clock to gp o 3, 2 , 1 respectively. t he c ontrol of the auxiliary clock is determined by r eg 18h t able 29 and reg19h t able 30 . i n general terms, this highly fexible clock source allows the selection of one of the various v co o r crystal related clocks inside the synthesizer or the selection of a fexible unstabilized auxiliary ring oscillator clock. a ny of the sources may be routed out via gpo_sel=7. a d ditional reg18h t able 29 clock controls allow the aux clock to be delayed by a variable amount (auxclk_modesel reg18h<3:2>) , or to be divided down by even values from 2 to 14 (auxclk_divsel reg18h<6:4>) . modulator outputs (gpo_sel=10) setting register gpo_ sel=10 ( reg1b<3:0> t able 32 ) assigns the three lsbs of the delta sigma modulator output to gp o <3:1>, where gp o 1 is t he lsb. t hi s feature allows the possibility of using the hm c 70 2lp6 c e as a g eneral purpose digital delta sigma modulator for many possible applications. external vco t he hm c 702lp6 c e i s targeted for ultra low phase noise applications with an external v co . t he synthesizer has been designed to work with v co s th at can be tuned nominally over 0.5 to 4.5 volts on the varactor tuning port with a +5v charge pump supply voltage. slightly wider ranges are possible with a +5.5v charge pump supply or with slightly degraded performance. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 14 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll external vco with active inverting opamp loop filter a n external opamp active flter is required to support external v co s wi th tuning voltages above 5v. i f an i nverting opamp is used with a positive slope v co , ph ase_sel r eg 05h <0> = 1 t able 11 must be set to invert the pfd phase polarity and obtain correct closed loop operation. figure 9. conventional synthesizer with vco temperature sensor t he hm c 702lp6 c e fe atures a built in temperature sensor which may be used as a general purpose temperature sensor. t he temperature sensor is enabled via tsens_spi_enable ( reg1eh=1 t able 35 ) and when enabled draws 2 m a . t he temperature sensor features a built in 3-bit quantizer that allows the temperature to be read in register tsens_ temperature ( reg21h t able 38 ). t he temperature sensor data converter is not clocked. updates to the temperature sensor register are made by strobing register tsens_spi_strobe ( r eg00h<3> t able 6 ). t he 3-bit quantizer operates over a -40 c to + 100 c r ange as follows: t n = foor {( t em perature +40) / 17.5 where t n is the decimal value of register tsens_temperature} (eq 7) 0 1 2 3 4 5 6 7 -40 -20 0 20 40 60 80 100 temperature (c) temperature sensor quantizer output figure 10. typical temperature sensor quantizer output t emperature sensor slope is 17.5 mv/lsb. a bs olute tolerances on the temperature sensor thresholds may vary by up to 10 c wo rst case. n ominal temperature is given by: (eq 8) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 15 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll charge pump & phase frequency detector (pfd) t he phase frequency detector or pfd has two inputs, one from the reference path divider and one from the v co p ath divider. t he pfd compares the phase of the v co p ath signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. t he o utput current varies linearly over a full 2 radians input phase difference. pfd functions phase_sel ( reg05h<0> t able 11 ) inverts the phase detector polarity for use with an inverting opamp or negative slope v co upout_en in reg05h<1> t able 11 allows masking of the pfd up output, which effectively prevents the charge pump from pumping up . dnout_en in reg05h<2> t able 11 allows masking of the pfd down output, which effectively prevents the charge pump from pumping down. charge pump tri-state de-asserting both upout_en and dnout_en effectively tri-states the charge pump while leaving all other functions operating internally. pfd jitter & lock detect background i n normal phase locked operation the divided v co s ignal arrives at the phase detector in phase with the divided crystal signal, known as the reference signal. despite the fact that the device is in lock, the phase of the v co signal and the reference signal vary in time due to the phase noise of the crystal and v co o scillators, the loop bandwidth used and the presence of fractional modulation or not. t he to tal integrated noise on the v co p ath normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. i f we wish to detect if the v co i s in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. first, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. t he standard deviation of the arrival time of the v co s ignal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked v co h as a constant phase noise, 2 (? 0 ), at offsets less than the loop 3 db bandwidth and a 20 db per decade roll off at greater offsets. t he simple locked v co phase noise approximation is shown on the left of figure 11. figure 11. synthesizer phase noise & jitter information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 16 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll with this simplifcation the single sideband integrated v co pha se noise, 2 , in rads 2 at the phase detector is given by (eq 9) where 2 ssb (? 0 ) is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, b is the 3 db corner frequency of the closed loop pll and n is the division ratio of the prescaler t he rms phase jitter of the v co i n rads, , results from the power sum of the two sidebands: = 2 2 ssb (eq 10) since the simple integral of (eq 9) is just a product of constants, we can easily do the integral in the log domain. for example if the v co p hase noise inside the loop is -100 dbc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio n =1 00, then the integrated single sideband phase noise at the phase detector in db is given by 2 db = 10log ( 2 (? 0 )b ? n 2 ) = -100 + 50 + 5 - 40 = -85 dbrads, or equivalently = 10 -82/20 = 56 urads rms or 3.2 milli-degrees rms. while the phase noise reduces by a factor of 20log n af ter division to the reference, the jitter is a constant. t he rms jitter from the phase noise is then given by t jnp = t ref / 2 i n this example if the reference was 50 mhz, t ref = 20 nsec, and hence t jpn = 178 femto-sec. a normal 3 sigma peak-to-peak variation in the arrival time therefore would be 3 2 t jpn = 0.756 ps i f the synthesizer was in fractional mode, the fractional modulation of the v co divider will dominate the jitter. t he exact standard deviation of the divided v co s ignal will vary based upon the modulator chosen, however a typical modulator will vary by about 3 v co p eriods, 4 v co p eriods, worst case. i f, for example, a nominal v co a t 5 ghz is divided by 100 to equal the reference at 50 mhz, then the worst case division ratios will vary by 1004. hence the peak variation in the arrival times caused by ? modulation of the fractional synthesizer at the reference will be (eq 11) pfd jitter and lock detect background (continued) i n this example, t j?pk = 200 ps(108-92)/2 = 1600 psec. i f we n ote that the distribution of the delta sigma modulation is approximately gaussian, we could approximate t j?pk as a 3 sigma jitter, and hence we could estimate the rms jitter of the ? modulator as about 1/3 of t j?pk or about 532 psec in this example. hence the total rms jitter t j , expected from the delta sigma modulation plus the phase noise of the v co wo uld be given by the rms sum , where (eq 12) i n this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation. bottom line, we have to expect about 1.6 nsec of normal variation in the phase detector arrival times when in fractional mode. i n ad dition, lower v co fr equencies with high reference frequencies will have much larger variations., for example, a 1 ghz v co o perating at near the minimum nominal divider ratio of 72, would, according to ( eq 11 ), exhibit about 4 nsec of peak variation at the phase detector, under normal operation. t he l ock detect circuit must not confuse this modulation as being out of lock. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 17 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll pfd lock detect lkd_en ( reg01h<11> t able 7 ) enables the lock detect functions of the hm c 70 2lp6 c e. t he lock detect circuit in the hm c 70 2lp6 c e pl aces a one shot window around the reference. t he o ne shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer. c learing lkd_ringosc_mono_select ( reg1ah<14> t able 31 ) will result in a nominal 10nsec analog window of fxed length, as shown in figure 12 . setting lkd_ringosc_mono_select will result in a variable length digital widow. t he d igital one shot window is controlled by lkd_ringosc_cfg (reg1ah<16:15> t able 31 ) . t he resulting lock detect window period is then generated by the number of ring oscillator periods defned in lkd_monost_duration reg1ah<18:17> ( t able 31 ). t he lock detect ring oscillator may be observed on the gp o 2 po rt by setting ringosc_testmode ( reg1ah<19> t able 31 ) and confguring the gpo_sel<3:0> = 0111 in ( reg1bh t able 32 ). lock detect does not function when this test mode is enabled. lkd_wincnt_max ( reg1ah<9:0> t able 31 ) defnes the number of consecutive counts of the v co t hat must land inside the lock detect window to declare lock. i f fo r example we set lkd_wincnt_max = 1000 , then the v co a rrival would have to occur inside the selected lock widow 1000 times in a row to be declared locked. when locked the lock detect fag ro_lock_detect ( reg1fh<0> t able 36 ) will be set. a single occurrence outside of the window will result in clearing the lock detect fag, ro_lock_detect . t he lock detect fag ro_lock_detect ( reg1fh<0> t able 36 ) is a read only register, readable from the serial port. t he lock detect fag is also output to the ld_sdo pin according to lkd_to_sdo_always (reg1ah<13>) and lkd_to_sdo_ automux_en (reg1ah<12>) , both in t able 31 . setting lkd_to_sdo_always will always display the lock detect fag on ld_dso . c learing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display the lock detect fag on ld_sdo except when a serial port read is requested, in which case the pin reverts temporarily to the serial data o ut pin, and returns to the lock detect function after the read is completed. figure 12. normal lock detect window lock detect with phase offset when operating in fractional mode the linearity of the charge pump and phase detector are more critical than in integer mode. t he p hase detector linearity is worse when operated with zero phase offset. hence in fractional mode it is necessary to offset the phase of the reference and the v co a t the phase detector. i n su ch a case, for example with an offset delay, as shown in figure 13, the mean phase of the v co will always occur after the reference. t he lock detect circuit window can be made more selective with a fxed offset delay by setting win_asym_enable and win_asym_up_select ( reg1ah<11> t able 31 ). similarly the offset can be in advance of the reference by clearing win_asym_up_select while leaving win_asym_enable reg1ah<10> set both in t able 31 . information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 18 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll figure 13. delayed lock detect window for most applications the analog one shot window is sufficient. t o d etermine the required lock detect one shot window size: r equired ld o ne s hot window = ( c p ph ase o ff set (ns) + 8x t vc o) x 1.3. cycle slip prevention (csp) when changing frequencies the v co i s not yet locked to the reference and the phase difference at the pfd varies rapidly over a range much greater than 2 radians. since the gain of the pfd varies linearly with phase up to 2, the gain of conventional pfds will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. t hi s phenomena is known as cycle slipping. c yc le slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in figure 14. c yc le slipping increases the time to lock to a value far greater than that predicted by normal small signal laplace analysis. t he hm c 702lp6 c e pf d features c yc le slip prevention ( c sp ), an ability to virtually eliminate cycle slipping during acquisition. when enabled, the c sp f eature essentially holds the pfd gain at maximum until such time as the frequency difference is near zero. c sp a llows signifcantly faster lock times as shown infigure 14. t he u se of the c sp f eature is enabled with pfds_rstb ( reg01<15> t able 7 ). t he c sp feature may be optimized for a given set of pll dynamics by adjusting the pfd sensitivity to cycle slipping. t hi s is achieved by adjusting pfds_sat_deltan ( reg1c<3:0> t able 33 ). c sp will cause the v co n d ivider to momentarily divide by a higher or lower n v alue in order to pull the divided v co phase back towards the reference edge. t he m aximum recommended v co n d ivider deviation is no more than 20% of the target n value programmed into r eg ister f. for example, if n =5 0 for the target frequency, then the c sp magnitude should be 10 or less so r eg ister 1 c h bi ts [3:0] would be programmed to a h. i n situations where the target n v alue is low, for example 36 the c sp b ehavior will be compromised because the minimum v co d ivide value is 32. figure 14. cycle slip prevention (csp) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 19 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll charge pump gain a simplifed diagram of the charge pump is shown in figure 15. c ha rge pump up and down gains are set by cp_ upcurrent_sel and cp_dncurrent_sel respectively ( reg07 t able 13 ). n ormally the registers are set to the same value. each of the up and d n c harge pumps consist of 5-bit charge pumps with lsb of 125 a . t he c urrent gain of the pump, in a mp s/radian, is equal to the gain setting of this register divided by 2. for example if both cp_upcurrent_sel and cp_dncurrent_sel are set to 01000 the output current of each pump will be 1m a a nd the gain kp = 1m a /2 radians, or 159 u a /r ad. charge pump gain trim i n most applications gain t ri m is not used. however it is available for special applications. each of the up and d n p umps may be trimmed separately to more precise values to improve current source matching of the up and d n v alues, or to allow fner control of pump gain. t he pump trim controls are 3-bits, binary weighted for up and d n , in cp_uptrim_sel and cp_dntrim_sel respectively ( r eg 08h t able 14 ). lsb weight is 14.7 u a , x0 00 = 0 trim, x001 = 14.7 ua added trim, x111 = 100u a . charge pump phase offset either of the up or d n c harge pumps may have a d c l eakage or offset added. t he l eakage forces the phase detector to operate with a phase offset between the reference and the divided v co i nputs. i t is r ecommended to operate with a phase offset when using fractional mode to reduce non-linear effects from the up and d n p ump mismatch. phase noise in fractional mode is strongly affected by charge pump offset. d c l eakage or offset may be added to the up or d n p umps using cp_upoffset_sel and cp_dnoffset_sel ( reg08 t able 14 ). t hese are 4 bit registers with 28.7u a l sb. maximum offset is 430u a . a s an example, if the main pump gain was set at 1m a , an o ffset of 373u a wo uld represent a phase offset of about (392/1000)*360 = 133 degrees. for best spectral performance in fractional mode the leakage current should be programmed to: r equired leakage c ur rent ( a ) = (2 .5e-9 + 8x t vc o) x fcomparison (hz) x c p cu rrent ( a ) cp offset leakage current should never exceed 25% of the programmed cp current. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 20 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll figure 15. charge pump gain, trim and phase offset control frequency programming t he hm c 702lp6 c e ca n operate in either fractional mode or integer mode. i n in teger mode of operation the delta sigma modulator is disabled. frequency programming and mode control is described below. fractional frequency t he fractional frequency synthesizer, when operating in fractional mode, can lock to frequencies which are fractional multiples of the reference frequency. fractional mode is the default mode. t o ru n in fractional mode ensure that dsm_integer_mode r eg12h<3> t able 24 is clear and dsm_rstb is set r eg01<13> t able 7 . t hen program the frequency as explained below: t he output frequency of the synthesizer is given by, f vco , where fractional frequency of vco (eq 13) where n int is th e integer division ratio, an integer number between 36 and 65,533 ( dsm_intg ( reg0fh t able 21 )) n frac is t he fractional part, a number from 1 to 2 24 ( dsm_frac reg10h t able 22 ) r is th e reference path division ratio, ( rfp_div_ratio reg03h<13:0> t able 9 ) f xtal is t he frequency of the crystal oscillator input (xs in o r x r ef figure 4 ) a s an example: f xtal = 50 m hz r = 1 f ref = 50 m hz information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 21 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll n int = 92 n frac = 1 (eq 14) i n this example the output frequency of 9,600,000,005.96 hz is achieved by programming the 16-bit binary value of 92d = 5 c = 0 000 0000 0101 1100 into dsm_intg . similarly the 24-bit binary value of the fractional word is written into dsm_frac , 1d = 000 001h = 0000 0000 0000 0000 0000 0001 example 2 : set the output to 12.600 025 ghz using a 100 mhz reference, r =2 . find the nearest integer value, n int , n int = 126, f int = 12.600 000 ghz t his leaves the fractional part to be f frac =25 khz (eq 15) since n frac must be an integer number, the actual fractional frequency will be 24,998.19 hz, an error of 1.81 hz. here we program the 16-bit n int = 126d = 7eh = 0000 0000 0111 1110 and the 24-bit n frac = 4194d = 1062h = 0000 0100 0001 0010 i n addition to the above frequency programming words, the fractional mode must be enabled using the frac register. o ther dsm confguration registers should be set to the recommended values. r eg ister setup fles are available on request. integer frequency t he synthesizer is capable of operating in integer mode. i n i nteger mode the digital ? modulator is normally shut off and the division ratio of the v co divider is set at a fxed value. t o r un in integer mode set dsm_integer_mode ( reg12h<3> t able 24 ) and clear dsm_rstb ( reg01h<13> t able 7 ). t hen program the integer portion of the frequency, n int , as explained by (eq 13), ignoring the fractional part. frequency hopping trigger i f the synthesizer is in fractional mode, a write to the fractional frequency register, reg10h t able 22 , will initiate the frequency hop on the falling edge of the 31 st clock edge of the serial port write (see figure 19). i f the integer frequency register, reg0fh t able 21 , is written when in fractional mode the information will be buffered and only executed when the fractional frequency register is written. i f the synthesizer is in integer mode, a write to the integer frequency register, reg0fh t able 21 , will initiate the frequency hop on the falling edge of the 31 st clock edge of the serial port write (see figure 19). power on reset (por) n ormally all logic cells in the hm c 70 2lp6 c e ar e reset when the device digital power supply, dvdd, is applied. t hi s is referred to as power o n r es et, or just p or . p or n ormally takes about 500us after the dvdd supply exceeds 1.5v, guaranteed to be reset in 1msec. o nc e the dvdd supply exceeds 1.5v, the p or will not reset the digital again unless the supply drops below 100mv. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 22 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll soft reset t he sp i r egisters may also be soft reset by an sp i w rite to strobe global_swrst_regs ( reg00h<0> t able 6 ). a ll other digital, including the fractional modulator, may be reset with an sp i w rite to strobe global_swrst_dig (reg00h<1> t able 6 ). hardware reset t he sp i r egisters may also be hardware reset by holding r s t b, p in 19, low. power down t he hm c 702lp6 c e ma y be powered down by writing a zero to reg01h t able 7 . i n power down state the hm c 70 2lp6 c e should draw less than 10u a . i t sh ould be noted that reg01h is the enable and r es et r eg ister which controls 16 separate functions in the chip. depending upon the desired mode of operation of the chip, not all of the functions may be enabled when in operation. hence power up of the chip requires a selective write to reg01 bits. a n easy way to return the chip to its prior state after a power down is to frst read reg01h and save the state, then write a zero to reg01h for reset and then simply rewrite the previous value to restore the chip to the desired operating mode. cw sweeper mode t he hm c 70 2lp6 c e fe atures a built in frequency sweeper function. t hi s function supports external or automatic triggered sweeps. t he m aximum sweep range is limited to 510 x fxtal/ r . fo r example, with a 10 mhz comparison frequency, the maximum sweep range is 5100 mhz. t he start and end frequency points must be within 5100 mhz of one another. for sweep operation the delta-sigma modulator mode should be feed forward ( r eg ister 12h bits [9:8] = 11) otherwise discontinuities may occur when crossing integer- n b oundaries (harmonic multiples of the comparison frequency). sweeper modes include: a. 2 -way sweep mode: alternating positive and negative frequency ramps. b. 1 -way sweep mode c. s ingle step r am p mode a pplications include test instrumentation, fm c w se nsors, automotive radars and others. t he p arameters of the sweep function are illustrated in figure 16 . cw sweeper mode (continued) t he sweep generator is enabled with ramp_enable in ( reg14h<1> t able 25) . t he sweep function cycles through a series of discrete frequency values, which may be a. s tepped by an automatic sequencer, or b. s ingle stepped by individual triggers in single step mode. t riggering of each sweep, or step, may be confgured to operate: a. v ia a serial port write to reg14h<2> ramp_trigg (if r eg 14h<2> = 0 ) b. a uto matically generated internally, c. t ri ggered via t t l in put on gp o 3 r eg 14h<5> = 1. sweep parameters are set as follows: i nit ial frequency, f o = c urrent frequency value of the synthesizer, ( eq 15 ) final frequency, f f = frequency of the synthesizer at the end of the ramp information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 23 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll t he frequency step size while ramping is controlled by rampstep , ( reg15h t able 26 ). fr equency step size ? step = rampstep ? f xtal / 2 23 ? r wh ere r i s the value of the reference divider ( rfp_div_ratio in t able 9 ) c learing or setting ramp_startdir_dn , ( reg14h<4> t able 25 ), sets the initial ramp direction to be increasing or decreasing in frequency respectively. setting ramp_singledir ( reg14h<7> t able 25 ), restricts the direction of the sweep to the initial sweep direction only. t he sweeper timebase t ref is the period of the divided reference, f pfd , at the phase detector t ref t he total number of ramp steps taken in a single sweep is given by ramp_steps_number in r eg 16h t able 27 . t he total time to ramp from f o to f f is given by t ramp = t ref ? ramp_steps_number t he fnal ramp frequency, f f , is given by ? ? = ? i + ? step ? ramp_steps_number sweeper action at the end of sweep depends upon the mode of the sweep: a. with both ramp_singledir and ramp_repeat_en disabled, at the end of the ramp time, t ramp , the sweeper will dwell at the fnal frequency f f , until a new trigger is received. t he next trigger will reverse the current sequence, starting from f f , and stepping back to f o . o dd triggers will ramp in the same direction as the initial ramp, even triggers will ramp in the opposite direction. b. with ramp_singledir enabled and ramp_repeat_en disabled, at the end of the ramp time, t ramp , the sweeper will dwell at the fnal frequency f f , until a new trigger is received. t he s econd trigger will hop the synthesizer back to the initial frequency, f o . t he third trigger will restart the sweep from f o . hence all odd numbered triggers will start a new ramp in the same direction as the initial ramp, even numbered triggers will hop the synthesizer from the current frequency to f o , where it will wait for a trigger to start a sweep. ramp busy i n all types of sweeps ramp_busy will indicate an active sweep and will stay high between the 1 st and n th ramp step. ramp_busy may be monitored one of two ways. ramp_busy is readable via read only register reg1fh<5> t able 36 . ramp_busy may also be monitored on gp o 2, h ardware pin 24, by setting reg1bh<3:0> =8h t able 32 . autosweep mode t he a utosweep mode is similar to figure 16 except that once started, triggers are not required. o nc e enabled, ( ramp_ repeat_en=1 reg14h<3> t able 25 ) the a utosweep mode initiates the frst trigger, steps n times, one step per ref clock cycle, and then waits for the programmed dwell period and automatically triggers the ramp in the opposite direction. t he sweep process continues alternating sweep directions until disabled. dwell_time ( reg17h t able 28 ) controls the number of t ref periods to wait at the end of the ramp before automatically retriggering a new sweep. 2-way sweeps i f ramp_repeat_en ( reg14h<3> t able 25 ) is cleared, then the ramps are triggered by a. writing to ramp_trigg ( reg14h<2> t able 25 ), if bit <2> = 0, or b. by rising edge tt l si gnal input on gp o 3, i f ramp_trig_ext_en is set, and gp o 3 is e nabled. a ll functions are the same in figure 16 for a utosweep or 2-way t ri ggered sweeps, the only difference is the trigger source is generated internally for autosweep, and is input via serial port or gp o 3 fo r triggered sweeps. sweep_busy will go high at the start of every ramp and stay high until the nth step in the ramp. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 24 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll figure 16. 2-way sweep control via trigger triggered 1-way sweeps 1-way sweeps are shown in figure 17. unlike 2-way sweeps, 1-way sweeps require that the v co h op back to the start frequency after the dwell period. t riggered 1-way sweeps also require a 3 rd trigger to start the new sweep. t he 3 rd trigger must be timed appropriately to allow the v co to s ettle after the large frequency hop back to the start frequency. subsequent odd numbered triggers will start the 1-way sweep and repeat the process. figure 17. 1-way sweep control information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 25 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll single step ramp mode a single step 1-way r am p is shown in figure 18. i n th is mode, a trigger is required for each step of the ramp. single step will function in either 1-way or 2-way ramps. similar to autosweep, the ramp_busy fag will go high on the frst trigger, and will stay high until the nth trigger. t he n +1 trigger will cause the ramp to jump to the start frequency in 1-way ramp mode. t he n +2 trigger will restart the 1-way ramp. figure 18. single step ramp mode t he user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. i f th e loop bandwidth in use is much wider than the rate of the steps then the locking will be very fast and the ramp will have a staircase shape. i f t he update rate is higher than the loop bandwidth, as is normally the case, then the loop will not fully settle before a new frequency step is received. hence the swept output will have a small lag and will sweep in a near continuous fashion. main serial port t he hm c 702lp6 c e fe atures a four wire serial port for simple communication with the host controller. r eg ister types may be r ead o nl y, write o nl y, r ea d/write or strobe, as described in the registers descriptions. t he synthesizer also features an auxiliary 3-wire serial port, known as the v co s erial port. t he v co s erial port is a write only interface from the synthesizer to an optional switched resonator v co t hat supports 3-wire serial port control. t ypical main serial port operation can be run with s c lk a t speeds up to 50 mhz. serial port registers are described in the section r eg i s t e r m a p. ld_sdo pin operation c onfguration of the ld_sd o pin requires manipulation of both r eg 2h[1:0] and r eg 1 a h [13:12], as follows: serial data output (sd o ) wh en a serial read occurs and high impedance at all other times: r eg2h[1:0] = 0x (x=dont care) r eg1 a h[13:12] = 0x (x=dont care) serial data output (sd o ) wh en a serial read occurs and ld status at all other times (ld_sd o p in automatically muxed between ld and sd o ): r eg2h[1:0] = 11 r eg1 a h[13:12] = 01 information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 26 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll serial port write operation a vdd = dvdd = 3v 10%, a g n d = dg n d = 0v table 4. timing characteristics parameter conditions min. typ. max units t 1 se n t o s c lk s etup time 8 nsec t 2 sd i t o s c lk s etup time 10 nsec t 3 sd i t o c lk hold time 1 0 nsec t 4 s c lk high duration 8 n sec t 5 s c lk low duration 8 n sec t 6 se n high duration 6 40 nsec t 7 se n low duration 20 n sec a typical w rit e cy cle is shown in figure 19. a. t he m aster (host) both asserts se n ( serial port enable) and clears sd i to i ndicate a w r it e cycle, followed by a rising edge of s c lk . b. t he s lave (synthesizer) reads sd i o n the 1st rising edge of s c lk af ter se n . sd i l ow initiates th e w ri t e cy cle (/w r ) c. h ost places the six address bits on the next six falling edges of s c lk , msb frst. d. s lave registers the address bits in the next six rising edges of s c lk ( 2-7). e. h ost places the 24 data bits on the next 24 falling edges of s c k, m sb frst . f. s lave registers the data bits on the next 24 rising edges of s c k (8 -31). g. s e n i s de-asserted on or after the 32nd falling edge of s c lk . h. t he 3 2 nd rising edge of s c lk c ompletes the cycle figure 19. serial port timing diagram - write ld status always: r eg2h[1:0] = 11 r eg1 a h[13:12] = 01 high impedance always: r eg2h[1:0] = 10 r eg1 a h[13:12] = xx (x=dont care) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 27 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll main serial port read operation t he synthesizer uses the multi-purpose pin, ld_sdo , for both lock detect and serial data o ut ( sd o ) fu nctions. t he registers lkd_to_sdo_automux_en (reg1a<12>) and lkd_to_sdo_always ( reg1a<13> t able 31 ) determine how the data o utput pin is muxed with the lock detect function. i f bo th of the registers are cleared, then the pin is exclusively sd o . i f automux is enabled, the pin switches to sd o w hen the r d fu nction is sensed on the 1st rising edge of s c lk . i f lkd_to_sdo_always is set, then the pin ld_sdo is dedicated for lock detect only, and it is not possible to read from the synthesizer. a typical r e a d cy cle is shown in figure 20. a. t he m aster (host) asserts both se n ( serial port enable) and sd i to i ndicate a r e a d cycle, followed by a rising edge s c lk b. t he s lave (synthesizer) reads sd i o n the 1st rising edge of s c lk af ter se n . sd i h igh initiates th e r e a d cy cle ( r d) c. h ost places the six address bits on the next six falling edges of s c lk , msb frst. d. s lave registers the address bits on the next six rising edges of s c lk ( 2-7). e. s lave places the 24 data bits on the next 24 rising edges of s c k (8 -31), msb frst . f. h ost registers the data bits on the next 24 falling edges of s c k (8 -31). g. s e n i s de-asserted on or after the 32nd falling edge of s c lk . h. t he 3 2nd falling edge of s c lk c ompletes the cycle figure 20. serial port timing diagram - read register map table 5. reg 00h chip id (read only) register bit type name width default description [23:0] ro c hip i d 24 581504h c hip i d table 6. reg 00h strobe (write only) register bit type name width default description 0 s t r gl obal_swrst_regs 1 0 strobe to soft reset the sp i r egisters 1 s t r gl obal_swrst_dig 1 0 strobe to soft reset the rest of digital 2 s t r mc nt_resynch 1 0 r es erved 3 s t r tse ns_spi_strobe 1 0 strobe to clock the temperature measurement on demand information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 28 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 7. reg 01h enable & reset register bit type name default description 0 r / w malg_vcobuf_en 1 1 v co buf fer enable 1 r / w mag_bias_en 1 1 bias enable. when 0 pll is disabled. 2 r / w rfp_div_en 1 0 enables / holds refdiv in reset holding r ef d ivider in reset is equivalent to bypassing the divider, see figure 4 3 r / w xrefmux_todig_en 1 1 enables clock gate for xtal muxed (sq or sin) reference to digital. program 1 4 r / w rfp_div_todig_en 1 1 enables divided reference clock to the digital see figure 4 5 r / w rfp_sqr_todig_en 1 0 enables square wave xtal clock to main digital see figure 4 program 0 6 r / w rfp_sin_todig_en 1 0 enables sine wave xtal clock to main digital see figure 4 7 r / w rfp_buf_sq_en 1 1 enables square wave r ef b uffer. a ls o requires r eg 3h[16]=0 for square wave r ef b uffer. see figure 4 8 r / w rfp_buf_sin_en 1 0 enables sine wave r ef b uffer also requires r eg 3h[16]=1 for sine wave r ef b uffer. see figure 4 9 r / w vcop_todig_en 1 1 1= divided v co a s digital, ? modulator clock 0= divided r ef p ath as the ? modulator clock program 1 10 r / w vcop_presc_en 1 1 enables the prescaler bias 11 r / w pfd_lkd_en 1 1 enable / r es etb to digital lock detect circuit and pfds lock detect output gates program 1 12 r / w cp_en 1 1 c ha rge pump enable, disable is tri-stated output 13 r / w dsm_rstb 1 1 1 - enables fractional modulator see also dsm_integer_mode reg12h<3> 14 r / w lkd_rstb 1 1 1 - enables lock detect circuit 15 r / w pfds_rstb 1 1 c sp p fd ff rstb 1 - enables the c yc le slip prevention ( c sp ) feature of the pfd (also need r eg 1 c [5 ]=1) table 8. reg 02h serial data out force register bit type name default description 0 r / w malg_sdo_driver_force_val 1 serial data o ut f orce value t hi s value may be forced onto ld_sd o b y setting malg_sdo_driver_force_en 1 r / w malg_sdo_driver_force_en 1 serial data o ut e n f orce enable places value from malg_sdo_driver_force_val on sd o information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 29 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 9. reg 03h reference path register bit type name default description 13:0 r / w rfp_div_ratio also referred to as r 1 di vides the crystal input by this number r if r fp_div_en=1 and rfp_div_select = 1 rfp_div_ratio = 0 not allowed 2<=div_ratio<=2^14 see figure 4 14 r / w rfp_div_select 0 1 = reference divider enabled 0 = bypass ref divider see figure 4 15 r / w rfp_auto_refdiv_sel_en 1 1 = auto ref divider enable or bypass is automatic if rfp_div_ratio = 1, bypass divider if rfp_div_bypass ~=1 use divider see figure 4 16 r / w rfp_buf_sin_sel 0 selects sine wave reference for normal operation a ls o requires r eg 1h[8:7]=10 for sine wave reference buffer operation. see figure 4 table 10. reg 04h prescaler duty cycle register bit type name default description 0 r / w vcop_dutycycmode 0 extends the low time from 30 to 94 v co c ycles for large divide ratios. program 0. table 11. reg 05h phase freq detector register (pfd) bit type name default description 0 r / w pfd_phase_sel 0 i nve rts pfd polarity 0 = passive filter +ve slope v co 1 = pa ssive filter -ve slope v co 1 = a ct ive inverting flter, +ve slope v co 0 = a ct ive inverting flter, -ve slope v co 1 r / w pfd_upout_en 1 a ll ows masking of the up outputs between pfd and c p 2 r / w pfd_dnout_en 1 a ll ows masking of the dn outputs between pfd and c p table 12. reg 06h phase freq detector delay register bit type name default description 2:0 r / w pfd_del_sel 2h delay line set point to pfd program 001 table 13. reg 07h charge pump up/dn control register bit type name default description 4:0 r / w cp_upcurrent_sel 10h sets c ha rge-pump up gain, 125u a l sb, binary, 4m a m ax program as needed 9:5 r / w cp_d n cur rent_sel 10h sets c ha rge-pump dn gain, 125u a l sb, binary, 4m a m ax program as needed information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 30 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 14. reg 08h charge pump trim & offset register bit type name default description 3:0 r / w cp_uptrim_sel 0 t ri m up gain, 14.3u a l sb, binary, 100u a m ax program 0 7:4 r / w cp_d n tr im_sel 0 t ri m dn gain, 14.3u a l sb, binary, 100u a m ax program 0 11:8 r / w cp_upoffset_sel 4h up o ffset leakage current, 28.7u a l sb, binary, 430u a m ax program as needed. see c ha rge pump phase o ff set section 15:12 r / w cp_d n off set_sel 0 dn o ffset leakage current, 28.7u a , b inary, 430u a ma x program as needed. see c ha rge pump phase o ff set section 17:16 r / w cp_amp_bias_sel 2h c ha rge pump dummy branch o p am p bias selection, 100u a p rogram 10 table 15. reg 09h charge pump en register bit type name default description 0 r / w cp_pull_updn_en 0 enables c p up /down c on trol r eg 09 [1] 1 r / w cp_pull_dn_upb 0 0 - forces c ha rge pump up when r eg 09[0]=1 1 - forces c ha rge pump d n w hen r eg 09[0]=1 table 16. reg 0ah reserved bit type name default description 23:0 r / w r es erved 304h r es erved table 17. reg 0bh reserved bit type name default description 23:0 r / w r es erved 0 r es erved table 18. reg 0ch reserved bit type name default description 23:0 r / w r es erved 100h r es erved table 19. reg 0dh reserved bit type name default description 23:0 r / w r es erved 20h r es erved table 20. reg 0eh reserved bit type name default description 23:0 r / w r es erved 0 r es erved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 31 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 21. reg 0fh integer division register bit type name default description 15:0 r / w dsm_intg c 8 h unsigned integer portion of v co d ivider value, also known as n int , see ( eq 12 ) table 22. reg 10h fractional division register bit type name default description 23:0 r / w dsm_frac 0 unsigned fractional portion of v co d ivider also known as n frac , see ( eq 12 ) table 23. reg 11h seed register bit type name default description 23:0 r / w dsm_seed 0 unsigned seed value for ? modulator sets the start phase of the modulator. use a random , non-repeating number for best results (examples: 3 a 19 53h, de a db eh, 50894 c h) table 24. reg 12h delta sigma modulator register bit type name default description 0 r / w dsm_ref_clk_select 0 use reference instead of divider program 0 1 r / w dsm_invert_clk_sd3 1 invert ? clk 2 r / w dsm_invert_clk_rph 0 inverts the ref clock phase 3 r / w dsm_integer_mode 0 1- enables i nt eger mode, bypasses the ? modulator, leaves it running see also dsm_rstb r eg 01h<13> to disable the modulator 4 r / w r es erved 0 5 r / w r es erved 0 6 r / w dsm_xref_sin_select 0 when xref is selected specifes that the sine source is used 7 r / w dsm_autoseed 1 automatic seed load when changing the frac part, uses value in seed 9:8 r / w dsm_order 2h delta-sigma modulator confguration: 00-1st order 01-2nd order 10-3rd order feedback 11-3rd order feedforward use either 10 or 11. for sweeper operation use 11 only. do not use 1st or 2nd order (for test only) 13:10 r / w dsm_quant_max 3h max value allowed out of ? modulator quantizer limits are +7 to -8, typ 3 or 4 program 3h 17:14 r / w dsm_quant_min c h m in value allowed out of ? modulator quantizer limits are +7 to -8, typ 3 or 4 program c h [1] phase-error measurement and c om pensation in pll frequency synthesizers for fm c w, s ensors i : c on text and a pp lication, pichler, stelzer, member, i ee e, seisenberger, and vossiek, i ee e t ra nsactions on c ir cuits and systems i , v o l. 5 4, n o. 5 , may 2007 information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 32 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 25. reg 14h cw sweep control register t he maximum sweep range is limited to 510 x fxtal/ r . de lta-sigma modulator mode should be feed forward when using sweep feature ( r eg ister 12h bits [9:8] = 11. bit type name default description 0 r / w clear_ovf_undf 0 asynchronous clear for ovf/undf fags 1 r / w ramp_enable 0 r a mp en/rstb 1= enables the c w r am p function 2 r / w ramp_trigg 0 write always triggers ramps if bit <2> = 0, if bit <2> = 1, r am p will not trigger, bit <2> must be reset to 0 frst 3 r / w ramp_repeat_en 0 r am p r ep eat seq enable 1= enables autotrigger of ramps 0 = ramp_trigg starts each ramp 4 r / w ramp_startdir_dn 0 r am p start direction 1= start with r am p down 0= start with r am p up 5 r / w ramp_trig_ext_en 0 enable hardware trigger on gp o 3 pi n 6 r / w ramp_singlestep 0 r am p single step, advances the ramp to the next step, and holds frequency 7 r / w ramp_singledir 0 r am ps in one direction only with hop to start at end of ramp table 26. reg 15h cw sweep ramp step register t he maximum sweep range is limited to 510 x fxtal/ r . de lta-sigma modulator mode should be feed forward when using sweep feature ( r eg ister 12h bits [9:8] = 11. bit type name default description 23:0 r / w ramp_step 800h r am p step size table 27. reg 16h cw sweep ramp step number register t he maximum sweep range is limited to 510 x fxtal/ r . de lta-sigma modulator mode should be feed forward when using sweep feature ( r eg ister 12h bits [9:8] = 11. bit type name default description 23:0 r / w ramp_steps_number 800h r am p n um ber of steps in ramp table 28. reg 17h cw sweep dwell time register bit type name default description 23:0 r / w ramp_dwell_time 800h r am p n um ber of cycles to hold at top/bottom in repeat mode information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 33 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 29. reg 18h auxiliary oscillator register 1 bit type name default description 1:0 r / w dsmclk_auxclk_insel 0 selects the input clk for auxclk program 0 0:vcodiv r ec ommended 1:xrefsq or sin 2:refdiv 3:ring oscillator from mono, est 300 mhz to 1 ghz 3:2 r / w dsmclk_auxclk_modesel 0 program 0 0: bypass-no delay 1: pass through w/ delay 2: ring-out constant 3: ring-out seeded/gated 6:4 r / w dsmclk_auxclk_divsel 2h divider selection auxclk value divby program 010 000 001 010 011 100 101 110 111 1 2 4 6 8 10 12 14 7 r / w dsmclk_auxclk_sel 1 selects auxclk (if=1) as natural reference clk input of sigma delta program 1 8 r / w dsmclk_auxmod_lfsr_en 0 enables 10-bit lfsr inside the delay modulator (clocked by auxclk or auxclkb) program 0 9 r / w dsmclk_auxmod_accum_en 0 enables 8-bit accumulator inside the delay modulator (clocked by auxclk or auxclkb) program 0 11:10 r / w dsmclk_auxmod_mode 0 delay modulation mode program 0 0: auxmod_lodly_in passthrough 1: accumulator based square-wave 2: lfsr (lo-amp) 3: lfsr (hi-amp) 19:12 r / w dsmclk_auxmod_fracstep 0 step-size of accumulator (changes square-wave value once it wraps through 256) program 0 22:20 r / w dsmclk_auxmod_lodly 0 value of delay-element (when auxmod_mode=0) or low value used during sq-wave modulation program 0 table 30. reg 19h auxiliary oscillator register 2 bit type name default description 2:0 r / w dsmclk_auxmod_hidly 7h high value of delay element during sq-wave modulation. program 7h 3 r / w dsmclk_auxmod_clkinv 1 optionally inverts auxclk as used by the modulator. program 1 4 r / w dsmclk_auxmod_clkwring 0 select lkd ringosc to clock the lfs r . pro gram 0 information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 34 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 31. reg 1ah lock detect register bit type name default description 9:0 r / w lkd_wincnt_max 40h threshold count in the timer window to declare lock (reference cycles) 10 r / w lkd_win_asym_enable 0 enables asymmetric lock detect window (nominal 10nsec) 11 r / w lkd_win_asym_up_select 0 sets polarity of the window 12 r / w lkd_to_sdo_automux_en 1 muxes the lkd output signal to sd o w hen sd o i s not being used for main serial port data o ut puts ( r ea d o per ation) 13 r / w lkd_to_sdo_always 0 muxes the lkd output signal to sd o a lways, not possible to do main serial port r ea d in this state 14 r / w lkd_ringosc_mono_select 0 1 select ringosc based oneshot for lock detect window 0 selects analog based oneshot 16:15 r / w lkd_ringosc_cfg 0 00 fastest 11 slowest 18:17 r / w lkd_monost_duration 0 00 shortest 11 longest 19 r / w lkd_ringosc_testmode 0 enables the ring osc by itself for testing information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 35 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 32. reg 1bh gpo control register bit type name default description 3:0 r / w gpo_sel 0 selects data to be driven on gp o p orts gpo_sel<3:0> = 0000 gp o 3 < =gposel_0_data<2> gp o 2 <= g posel_0_data<1> gp o 1 <= g posel_0_data<0> gpo_sel<3:0> = 0001 gp o 3 <= x ref_clk_in gp o 2 <= r ef_clk_in gp o 1 < = vco_div_clkin gpo_sel<3:0> = 0010 gp03 <= pfd_up_in gp02 <= pfd_dn_in gp01 <= lkd_monost_window gpo_sel<3:0> = 0011 gp03 <= pfd_sat_ref_in gp02 <= pfd_sat_vco_div_in gp01 <= delta_integer_cycslip_sel, this strobe holds the gain of the pfd at max for anti-cycle slipping gpo_sel<3:0> = 0100 gp03 <= xref_clk_in gp02 <= xref_sin_in gp01 <= sd_frac_strobe_sync, internally synchronized frac strobe gpo_sel<3:0> = 0101 r es erved gpo_sel<3:0> = 0110 gp03 <= sd_ i nt z1<1> gp02 <=sd_ i nt z1<2> gp01 <= sd_ i nt z1<3> 3-bit quantized version of the v co p hase gpo_sel<3:0> = 0111 gp03 <= aux_clk gp02 <= ringosc_test gp01 <= clk_sd gpo_sel<3:0> = 1000 gp03 <= 00 gp02 <= ramp_busy gp01 <= r es erved gpo_sel<3:0> = 1001 n o t used gpo_sel<3:0> = 1010 gp03 <= ? quantizer o ut put 3rd lsb gp02 <= ? quantizer o ut put 2nd lsb gp01 <= ? quantizer o ut put lsb 6:4 r / w gpo_sel_0_data 0 this data is driven on gpo if gpo_sel==0 7 r / w gpo_dig_drive_en 0 enables t ri -state drivers on gp o o utput pads 10:8 r / w gpo_ind_drive_dis 000 000 = all gp o p ad drivers enabled xx1 = disable gp o 1 pa d driver x1x = disable gp o 2 pa d driver 1xx = disable gp o 3 pa d driver information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 36 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll table 33. reg 1ch phase detector csp register bit type name default description 3:0 r / w pfds_sat_delta n 0 0= c yc le slip prevention ( c sp ) disabled 4-bit value to advance or retard phase detector in v co c ycles if it reaches 2pi , i.e. cycle slip prevention. 1st bit is polarity, enabled by rstb 4 r / w pfds_rstb_force 0 c sp p fd flip-fops r s t b: 1 - c ontrolled by the pfds_rstb bit: 0 - auto-controlled by the c sp l ogic forces the pfd into reset, which tri-states charge pump, freezes charge on the loop flter, and hence opens the loop. program 0 5 r / w pfds_rstb 1 c sp p fd ff rstb 1 - enables the c yc le slip prevention ( c sp ) feature of the pfd (also need r eg 1 [15]=1) table 34. reg 1dh reserved bit type name default description 23:0 ro r es erved 0 r es erved table 35. reg 1eh temperature sensor register bit type name default description 0 r / w tsens_spi_enable 0 enable the temperature sensor, draws ~2m a c urrent, must strobe tsens_spi_strobe r eg 0 0h <3> table 36. reg 1fh ld, vco & ramp busy read only register bit type name default description 0 ro ro_ lock_detect 0 1 = locked, 0 = unlocked 3:1 ro ro_d sm_overfow 0 1 = modulator overfow 4 ro r es erved 0 r es erved 5 ro ro_ ramp_busy 0 sweeper status fag, set when ramp is busy, cleared when at end of ramp or not used table 37. reg 20h reserved bit type name default description 23:0 ro r es erved 20h r es erved table 38. reg 21h temperature sensor read only register bit type name default description 6:0 ro tse ns_temperature 1fh c urr ent t emp erature from temp sensor lsb = 17.5 c 00 00111 = t em p >= 82.5 c 00001 10 = t em p 0000000 = t em p <=-22.5 c tse ns_temperature = foor (( t em p+40)/17.5) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 37 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll outline drawing not es: 1. p ac k a ge b o dy m at e ri a l: l o w s tr es s i n je c tion m o ld ed pl a s tic s i l ic a a n d s i l ic on i mp r eg na t ed . 2. le a d a n d g ro u n d p a ddl e m at e ri a l: co p pe r a ll o y. 3. le a d a n d g ro u n d p a dd le pl at in g: 1 00% m at t e t in . 4. d i me n s io n s a r e i n i nc he s [m i ll i me t e r s] . 5. le a d sp ac in g to le ra nc e i s n on - c um ul at i ve . 6. p a d bu rr l e n g t h sh a ll b e 0.15mm m a x. p a d bu rr h e i gh t s h a ll b e 0.25mm m a x. 7. p ac k a ge w ar p sh a ll n ot e x c ee d 0.05mm 8. a ll g ro u n d le a ds a n d g ro u n d p a dd le mus t b e s o ld e r ed to p c b r f g ro u n d. 9. r efe r to h it tit e a pp l ic ation n ot e f or s ugges t ed p c b l an d p at t e rn . part n umber package body material lead finish msl r ating package marking [1] hm c 702lp6 c e r ohs-compliant low stress i nj ection molded plastic 100% matte sn msl1 [2] h702 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c package information table 39. reg 22h reserved bit type name default description 23:0 ro r eserved 0 r eserved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pll - fractiona l - n - s m t 38 HMC702LP6CE v10.0812 14 ghz 16-bit fractional-n pll information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d

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